This invention relates to a digital exchange technique and, more particularly, to a reception-synchronization protecting device and a reception-synchronization protecting method used in a common line signaling technique. In the common line technique, speech and data information and a control signal are separated and then transmitted over a separately arranged speech line and a signal line when a plurality of exchanges are connected through a communication network.
Along with today's rapid advancement of a multimedia communication, such as the Internet, the common line signaling technique has dramatically advanced. In the common line signaling technique, speech and data information and a control signal are separated and then transmitted over a separately arranged speech line and a signal line to each other when a plurality of exchanges are connected through a communication network. Japanese Unexamined Patent Publication (A) No. 8858/1997 discloses such conventional common line signaling techniques.
In this disclosed conventional art, a timing reproducing circuit reproduces a clock signal from carrier data signals that have arrived at a hub station in a burst form in different phases from a plurality of terminals. The timing reproducing circuit comprises a level detector circuit, a carrier demodulator circuit, a gating circuit, a digital phase-locked loop (DPLL) circuit, and a discrimination circuit.
The level detector circuit is used for detecting the arrival of a carrier data signal and outputting a control signal. The carrier demodulator circuit is used for demodulating the carrier data signal into a baseband burst data signal. The gating circuit is used for extracting a particular signal from the demodulated baseband burst signal. The DPLL circuit is used for reproducing a clock signal in synchronization with the baseband burst data signal, using the particular signal. The discrimination circuit is used for discriminating the baseband burst data signal using the reproduced clock signal.
The baseband burst data signal from each terminal includes a preamble (PR) signal for establishing a bit synchronization, a unique word signal for establishing a frame synchronization, and data signal bearing information. The particular signal is the preamble signal.
According to the disclosure, since the gating circuit extracts the PR signal from the baseband burst data signal using the control signal, and by adding only the PR signal to the DPLL circuit, a timing reproduction is reliably performed without erratic frame synchronization in a guard time.
In the conventional art, it is however unknown what frequency a reception signal firstly exists when an initial synchronization is going to be established. To settle this, the reception signal is firstly detected so that synchronizations of a frequency and a clock timing are established early. In this event, if a synchronization frame (timing frame) to be synchronized suffers from a timing error, the power of a synchronization signal is reduced. In particular, when a synchronization timing is delayed caused by the timing error, a CCS (Common Line Signal) signal contained in a received frame is affected by a frequency estimating signal contained in the received frame. Namely, the frequency estimating signal partially overlaps onto the CCS signal so as to make an overlapped part in the CCS signal. The overlapped part becomes a noise component for the received frame. As a result, the received signal is reduced in a relative S/N (signal-to-noise) ratio.